This invention relates generally to floating gate memory devices such as an array of Flash electrically, erasable programmable read-only memory (EEPROM) cells. More particularly, the present invention relates to a tracking circuit and a method for use in an array of Flash EEPROM memory cells for performing an erase verify/erase operation so as to prevent an over-erasure problem.
As is generally well known in the art, electrical programmable and erasable memory array devices using a floating gate for the storage of charges thereon (Flash EPROMs/EEPROMs) have emerged in recent years. In a conventional EEPROM memory device, a plurality of one-transistor memory cells may be formed on a semiconductor substrate in which each cell is comprised of a P-type conductivity substrate, an N-type conductivity source region formed integrally within the substrate, and an N-type conductivity drain region also formed integrally within the substrate. A floating gate is separated from the substrate by a thin dielectric layer. A second dielectric layer separates a control gate from the floating gate. A P-type channel region in the substrate separates the source and drain regions.
In order to program the EEPROM cell, the drain region and the control gate are raised to predetermined potentials above the potential applied to the source region. For example, the drain region has applied thereto a voltage of approximately +5.0 volts with the control gate having a voltage of approximately +8.5 volts applied. These voltages produce "hot electrons" which are accelerated across the thin dielectric layer and onto the floating gate. This hot electron injection results in an increase of the threshold of the device by approximately two to four volts.
In order to erase the EEPROM cell, a relatively high positive potential (e.g., +5.0 volts) is applied to the source region. The control gate has applied thereto a negative voltage of -8.5 volts, and the drain region is allowed to float. A strong electric field develops between the floating gate and the source region, and negative charges are extracted from the floating gate to the source region by way of Fowler-Norheim tunneling.
In order to determine whether the EEPROM cell has been programmed or not, the magnitude of the read current is measured. Typically, in the read mode of operation, the source region is held at a ground potential and the control gate is held at a potential of about +4.2 volts. The drain region is held at a potential between 1 to 2 volts. Under these conditions, an unprogrammed or erased cell (storing a logic "1") will conduct a predetermined amount of current. On the other hand, the programmed cell (storing a logic "0") will have considerably less current flowing.
In addition, prior to the conventional erasing mode of operation in the array of Flash EEPROM memory cells, all of the cells are initially programmed to zero. Then, an erase verify operation is performed to determine if there are any memory cells that need to be erased (e.g., memory cells having a programmed threshold level or logic "0"). If one or more cells are found to exist that require erasing, an erase pulse is applied using a negative gate erase in accordance with Fowler-Norheim tunneling so as to discharge the charges on the floating gate of the memory cells. Thereafter, another erase verify operation is performed to check that the memory cells have been erased. This cycle of erase verify, erase pulse, and erase verify is repeated over and over until all of the cells in a sector have been successfully erased.
Unfortunately, the erase pulse is applied not only to the memory cell or bit that requires erasing, but to all of the bits in the same sector. As a result, all of the bits in the same sector, even those bits that have passed the erase verify operation, will receive the erase pulse and thus will become over-erased. Therefore, even with the control gate being grounded the over-erased bit or cell will always be turned ON which causes column leakage so as to prevent the proper reading of another cell in the column of the array containing this cell as well as making programming of the other cells on the same column increasingly more difficult. Further, in view of the fact that all of the bits in the same sector will not have the same rate of erasure, it is generally desirable to be able to determine which ones are the "slow" bits which will require a longer time to be erased.
Accordingly, in order to identify those "slow" bits during production, a procedure is currently being used by production engineers and testers which is referred to as "diagonal erase verify." This diagonal erase verify procedure is very similar to the conventional erase verify operation, except that the erase verify operation is performed only on the bits residing along the diagonal line of the sector. The total number of erase pulses required to pass the diagonal erase verify procedure is maintained. While it is known that all of the bits along the diagonal line have passed the erase verify, it is still not known whether the other bits have passed.
It has been empirically determined that the remainder of the bits in the same sector should pass the conventional or normal erase verify operation when less than 50% of the total number of erase pulses required to pass the diagonal erase verify are applied to the sector. By limiting the total number of erase pulses applied to the same sector to be less than 50% of the diagonal erase pulses, then the problem of over-erasure will be avoided so as to prevent other problems during the reading, verifying and programming modes of operation. This diagonal erase verify is performed currently on a separate test fixture.
In order to simplify the production process, the inventor of the present invention has developed a way of implementing the same function on the same semiconductor integrated circuit containing the memory device. This is accomplished by the provision of a tracking circuit which limits the total number of erase pulses applied to the same sector to be less than 50% of the diagonal erase pulses. Since the percentage of 50% of the diagonal erase pulses is a number determined by experimental investigation, it would be expedient to be able to vary the percentage from approximately 30% to 70% of the total diagonal erase pulses.